AMD’s 3D V-Cache marks the company’s first foray into 3D packaging, and the company shared more details behind its manufacturing process in a demonstration on Hot Chips 33. As a quick review, 3D V-Cache uses a novel fusion technology with additional 64MB 7nm SRAM cache stacked vertically on top of the Ryzen computing chiplets, which triples the number of L3 caches per Ryzen chip.
This new technology can provide up to 192MB of L3 cache for each chip, and AMD demonstrated that Ryzen 9 5900X uses the new cache to achieve a 15% performance improvement in 1080p games, which is roughly the performance we can get from the new cache . CPU microarchitecture and/or process node. However, AMD accomplished this feat using the same 7nm node and Zen 3 architecture as the standard Ryzen 5000 model. This progress is also accompanied by a single die stacked on top of the chip-AMD says it can stack more than one layer in the future, which will further increase capacity.
AMD revealed after the presentation that it can achieve similar output to the standard Ryzen model through the new 3D V-Cache chip, which means that it has crossed the barriers required to bring the chips. These chips will be put into production by the end of this year. .
AMD uses TSMC’s SoIC process to fuse the SRAM chiplet on top of the computing chip with the direct copper-to-copper dielectric bonding of the TSV connecting the two chips. This technology does not use solder micro-bumps to connect two chips, thus achieving a denser and more efficient interconnection. The interconnection density is 200 times that of a 2D chiplet.
TSMC uses two-phase bonding technology to fuse the two chips together. The first stage uses a hydrophilic dielectric-to-dielectric bonding process at room temperature, and then annealing and bonding the dielectric connection. The second stage is direct copper-to-copper bonding through solid-state diffusion to form bonds. AMD said that the technology uses a manufacturing technology similar to that of a silicon fab, and the back end is similar to TSV, which means that the production process is similar to that of conventional chips.
AMD keeps the SRAM chip in the center of the underlying L3 cache to reduce the heat exposure of the SRAM to the CPU core. In addition, AMD uses the same hybrid bonding process to place structural silicon on the CPU core, thereby creating a uniform height for the small chips and helping to cool the chips.
Compared with the micro-bump 3D connection, AMD stated that the interconnection efficiency of 3D V-Cache is three times that of interconnection efficiency, the energy consumption per bit is less than one-third, the interconnection density is increased by 15 times, and the interconnection efficiency is better. Power transfer characteristics.
AMD’s approach provides 2 TB/s of throughput between the two chips. The company stated that the latency impact is small and within the standard range of higher capacity L3 caches (the original access time of the cache expands with capacity).
The first graph shows the interconnection density between three different interconnection methods. Although AMD’s new interconnect has a 9 micrometer (μm) pitch (the distance between TSVs), the standard C4 package has a pitch of 130 microns, while the Microbump 3D has a pitch of 50 microns.
In contrast, the first-generation EMIB shipped by Intel has a pitch of 55 microns, while the second-generation EMIB that will be launched in 2023 has a pitch of 45 microns. However, Intel’s upcoming Foveros Direct is the most directly comparable interconnect technology, and Intel claims that its pitch will be less than 10 μm when it goes on the market at the end of 2023. At the same time, TSMC’s 9 μm hybrid bonding will launch AMD’s 3D V-Cache processor early next year.
AMD’s current memory logic is just the beginning of a broader trend in the industry. As the TSV pitch improves in successive generations of technology, it will unlock other finer stacking technologies, such as DRAM/HBM on the CPU, and stacking the entire CPU on top of the CPU.
Further development can find more refined methods, such as stacking CPU cores on top of other cores and stacking cores on top of non-cores (Intel has already done this in Lakefield). Furthermore, we can see macro-to-macro stacking, which means that various elements of the core micro-architecture are stacked on top of each other, even IP folding/split and circuit slicing.
Naturally, these distant technologies have not yet appeared on the drawing board, which will bring many challenges, especially in terms of heat dissipation, but AMD and other companies do see these technologies appear in the future.