AMD announced its 3D V-Cache technology a few months ago, demonstrating incredible performance improvements by simply stacking more L3 caches (up to 64MB) on top of Ryzen CPUs.Now thanks Yuzo Fukuzaki from TechInsights, We have more details about 3D V-Cache. This includes data showing that modern Zen 3 CPUs were designed to accommodate stacked 3D caches from the beginning, which tells us that this technology has been in use for many years.
According to Fukuzaki, he found connection points and 3D stack buffer space on a standard Ryzen 9 5950X sample. Looking at the picture below, you can see the points on the edge of the Zen 3 chip, which can be connected to the 3D V-Cache. If you want to install another 3D cache stack, these are copper connection points.
This mounting process uses TSV (Through Silicon Via) to fix the second layer of SRAM to the chip through hybrid bonding. Since TSV uses copper instead of solder, SRAM has a higher bandwidth and thermal efficiency than simply soldering the chips together.
According to their analysis, the company reverse-engineered some details behind the 3D V-Cache connection method, including TSV spacing, empty space inside the CPU for another cache stack, and so on.
- TSV pitch; 17μm
- KOZ size; 6.2 x 5.3 microns
- Rough estimate of TSV count; about 23,000! !
- TSV process position; between M10-M11 (a total of 15 metals, starting from M0)
All this confirms that AMD has been planning to implement 3D V-Cache for some time, so it can release updated Zen 3 components later this year. Thanks to this technology, the cache has increased significantly, which makes perfect sense— —The company apparently laid the foundation a few years ago.
It is also logical to expect AMD to use 3D V-Cache in its future architectures, such as the upcoming new Zen 4 architecture. 3D V-Cache will give AMD CPUs a huge advantage over Intel in terms of the original L3 cache size (at least for now), which becomes more and more important as the number of CPU cores increases.