Ascenium is one of the startups making waves in the field of CPU and general computing design. The company is helmed by CEO and co-founder Peter Foley, who has worked for Apple’s Apple I and Apple II computers and a long list of companies focused on hardware design. Ascenium recently received US$16 million in funding through its Series A financing-a clear demonstration of its belief in the company’s mission. What is the mission?
Pass the first to surpass the existing CPU architecture in terms of performance and power efficiency Software-defined processor.
Ascenium hopes to achieve this through the perfect combination of software and hardware implemented in its Aptos processor-by terminating the deep pipeline associated with today’s best-performing CPU, and creating a true, compiler-driven one based on the LLVM compiler Parallel processing CPU architecture. The Aptos processor that the company is currently developing is based on a 128-core general-purpose simple kernel array with 64-bit capabilities.If you remember Intel’s (now cancelled) efforts Xeon Phi Architecture, Ascenium’s Aptos is essentially the same many-core design paradigm, but it avoids the x86 instruction set (and its restrictions and requirements on the core design), and at the same time deploys a high-performance compiler that can be parallelized on its hardware resources Work load.
Ascenium has obtained 9 patents related to its architecture and software design, which will provide the company with much-needed defenses against those entrenched computing giants that will not/cannot give up their current instruction sets-such as x86 and Arm-and will likely Will hunt down an emerging participant whose product is sufficient to threaten the 50-year-old mature ISA we currently know.
The deep pipeline (essentially the routing instructions within the CPU architecture until the solution to the current problem is generated) allows to improve the performance of workload serialization-but negates many scenarios where parallelization (and thus higher performance) can be achieved. With the help of deep pipelines and dedicated hardware registers and stages that make up modern CPU processing, Ascenium estimates that about 50% of instructions are related to data movement through the pipeline-instructions and movement occupy processing time and power budget. Embedded in the architecture based on compilation The idea of the software solution of the processor will theoretically allow the Aptos processor to interpret workload instructions and allocate them to processing resources, so that the parallelized workload is as close to the theoretical maximum as possible, and at the same time, it has more advantages than instruction-based processors. Fewer architectural inefficiencies. Ascenium plans to push for a higher power/performance ratio-even a 10% saving in this equation is gold for both hyperscalers and the types of data center clients that Ascenium hopes to introduce into its ecosystem first. They are the ones who benefit most from this structure.
Naturally, if an architecture can be created to reduce the need for shuffling data, then it will find itself with related energy efficiency advantages. Then there is the structural weakness of x86, which requires too many transistors on a given problem to achieve a small amount of performance improvement-Ascenium CEO Peter Foley places it on the order of billions of transistors to achieve performance and sometimes even no performance Will enter the double-digit field of increase.
Therefore, Ascenium plans to abolish the instruction set, create the world’s first isomorphic, no instruction set and architecture processor, and usher in a new processing architecture built from the ground up. These are lofty goals-the risks are huge. But then again, so are rewards.