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Four-layer 3D stacking technology enables future chips

The true next-generation 3D chip stacking may be just around the corner, because research from the Institute of Microelectronics (IME) has just achieved a technological breakthrough that can stack up to four semiconductor layers.Compared with the traditional 2D manufacturing technology, this can save up to 50% of the cost, and the technology is likely to be used Best CPU with Best graphics card s future.

This achievement is a further improvement of AMD’s announcement of the TSMC-enabled SRAM stack, which will surely add luster to our computer before the end of this year, because this particular process currently only supports two chips (in AMD’s case, Zen 3 CCX is bound together on the first layer and the second layer 96MB SRAM cache. IME researchers demonstrated a process in which they successfully bonded four independent silicon layers through TSV (Through Silicon Via). These information highways allow communication between different chips.

AMD’s Lisa Su has a Ryzen 9 CPU with vertically stacked SRAM. (Image source: AMD)

TSVs and the active wafer stacks they enable are hailed as one of the most important technological breakthroughs to maintain (and possibly even improve) Moore’s Law, because they allow a wider information bus, which does not need to operate at extremely high frequencies to achieve performance goals . This, in turn, enables denser designs, because some components that were previously arranged horizontally can now be stacked vertically. It also allows for higher power efficiency, more effective heat dissipation, and even provides improved yields. The last point is because, for example, the different components that go into the CPU can now be manufactured on different wafers instead of the old, monolithic method, which automatically increases the ability to recover from manufacturing defects.

Bonding four-layer 3D silicon stack

A (very simplified) three-step process of bonding and actively connecting a four-layer 3D silicon stack. (Image source: IME)

The manufacturing method implemented by IME is “…by combining face-to-face and back-to-back wafer bonding with one-step TSV after stacking”. This means that the “face” of the first layer faces the second layer, and the second layer also faces it; the “back” of the second layer faces the back of the third layer, and the back of the third layer faces the face of the fourth layer. After these layers are bonded, the IME then “punches” them by etching along a specially designed path, which eventually becomes the TSV through which the data flows.

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