Intel confirms HBM memory for Sapphire Rapids, detailing the Ponte Vecchio package
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Intel issued a series of announcements at today’s International Supercomputing (ISC) 2021 conference, discussing its extensive solutions for supercomputing and HPC applications. The big news in hardware is that Intel’s Sapphire Rapids data center chip will be equipped with HBM memory, DDR5, PCIe 5.0 and support CXL 1.1.In addition, Intel confirmed that its Old Bridge GPU The OAM form factor will be adopted, and the power consumption of each package is said to be as high as 600W. Ponte Vecchio GPUs will appear in clusters of four or eight GPUs.
Intel Xeon Sapphire Rapids with HBM (High Bandwidth Memory)
Intel has leaked a lot of information about its Sapphire Rapids Xeon server chip, some intentionally and some unintentionally.We already know that the chip will follow Golden Bay Building Etched on 10nm enhanced SuperFin process.Intel Powering the chip for the first time in June 2020, They have DDR5, PCIe 5 and CXL 1.1 support, and will enter the Eagle Stream platform. These chips also support Intel Advanced Matrix Extensions (AMX), which is designed to improve the performance of training and inference workloads.
Intel has now revealed that these chips will be equipped with HBM memory, although the company did not specify how much capacity the chips will support or what type of memory they will use. This additional memory will be in the same package as the Sapphire Rapids CPU core, but it is unclear whether the HBM is located under the heat sink or connected as part of a larger package.
Intel has confirmed that these chips will be available to all its customers as part of the standard Sapphire Rapids product stack, although they will be available a bit later than the HBM-free variant, but at roughly the same time.
Intel has not disclosed how to expose HBM to the operating system: it can be imagined that this can be used as an L4 cache or as an accessory to standard main memory.However, Intel did reveal that these chips can be used with or No Main memory (DDR5), which means there may be multiple memory configuration options.
Intel said that HBM memory will help handle memory-bound workloads that are less sensitive to the number of cores, which may indicate that these chips will have fewer cores than standard models. Considering that HBM may need to be accommodated under the same radiator, this makes sense. Target workloads include computational fluid dynamics, climate and weather forecasting, artificial intelligence training and reasoning, big data analysis, in-memory databases and storage applications.
Intel has not disclosed more details, but recent leaks indicate that the chip will 56 cores and 64GB HBM2E memory in a Multi-chip packaging EMIB interconnection with the die.
Intel Ponte Vecchio OAM form factor
Intel announced its Xe HPC chip, used to create 47 Ponte Vecchio chips with 100 billion transistors, And is now being verified against the system in the new multi-GPU implementation. In addition, the company also said that these chips will adopt OAM (Open Accelerator Module) form factor, Confirm previous report.
The OAM form factor is designed for use in the OCP (Open Computing Platform) ecosystem. It consists of a GPU chip mounted on a carrier and then connected to the motherboard through a mezzanine connector.This arrangement is similar to Nvidia’s SXM form factor.
These types of chip packages are More common in servers Compared with add-on card form factors, because they allow for a more powerful cooling system than traditional card form factors, they also provide an optimized method of routing power to the OAM package through the PCB (as opposed to PCIe wiring).
The leaked Intel document lists the Ponte Vecchio OAM package with a peak of 600W, All signs indicate that at least some GPU models use liquid cooling. However, it is conceivable that the lower power variant may have an air cooling option.
Intel will provide nodes with four or eight OAM packages installed, called x4 or x8 subsystems. These nodes will then be integrated into their customers’ servers. Intel is currently validating these multi-GPU designs.
The first batch of Ponte Vecchio GPUs will appear in the Department of Energy’s Aurora Supercomputer, But the exascale system has been delayed several times (six years and continues), the latest one was caused by Intel’s 7nm delay, which eventually led to TSMC’s production of 16 Ponte Vecchio computing blocks.You can read more about the design Here.
Intel confirmed that Aurora does not use the aforementioned x4 or x8 form factor-each Aurora blade will consist of six Ponte Vecchio GPUs and two Sapphire Rapids CPUs (3:1 ratio).Intel also won another victory with Ponte Vecchio SuperMUC-NG supercomputer in Munich, GermanyThe system will have 240 new nodes, among which Ponte Vecchio is paired with Sapphire Rapids, but it is not clear whether these nodes use x4 or x8 sleds.
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