Comparison reviews

Introduced DDR5/DDR4 solutions for 5nm SoC

Synopsys has begun to provide its DDR5/DDR4 physical interface (PHY) and controller for the next-generation system-on-chip (SoC), which will be manufactured using TSMC’s N5 (5 nm) manufacturing technology. IP packaging enables SoC manufacturers to add support for these two types of memory on their chipsets manufactured using TSMC’s N5 node. Synopsys is the first IP company to provide a memory solution that supports DDR4 and DDR5 with a data transfer rate of up to 6400 MT/s.

Synopsys’ DesignWare IP package for DDR5/DDR4 memory implementation is quite advanced.It includes a DDR5/DDR4 controller It has a command scheduler, memory protocol handler, optional ECC, dual-channel support, and DFI 5.0 interface to its PHY. The module supports 64 CAM entries for reading, 64 CAM entries for writing, and a delay as low as 8 clock cycles. The controller can be programmed using Arm’s AMBA 3.0 APB interface.In addition, the company also provides its Silicon-proven DDR5/DDR4 physical layer (pass Design and reuse) Supports data transfer rates up to 6400 MT/s and a memory subsystem with up to four physical ranks. Obviously, both the controller and PHY support all the JEDEC standard functions of DDR4 and DDR5.

The IP package provided by Synopsys allows developers of various chips (CPU, SoC, SSD controller, etc.) to put the controller IP and physical interface into their N5 design, and then use the verification IP provided by the company to verify that everything is working properly.

(Image source: Synopsys)

With the introduction of each generation of products, memory support has become more complicated, and it has been difficult to support different types of memory with one design. Intel intends to support DDR4, DDR5, and (possibly) LPDDR4/LPDDR5 in its upcoming products Alder Lake processor. However, Intel has a lot of resources and can implement the controller and PHY itself. Smaller manufacturers tend to license such IP.

Related Articles

Leave a Reply

Your email address will not be published. Required fields are marked *

Back to top button