During a recent visit to the Intel Israel Lab, Gregory M Bryant, Executive Vice President and General Manager of Intel’s Client Computing Division, took some photos and then shared them on Twitter.According to Anandtech, one of the tweets (which were later deleted) appeared to display a poster on the office wall containing information about the unannounced Thunderbolt 5 protocol.
The poster says that Intel’s goal is “80G PHY technology”, which means it wants to achieve 80 Gbps connection, which will be twice the bandwidth of today Thunderbolt 4 and USB 4 connect. The poster also said that “USB 80G is designed to support the existing USB-C ecosystem”, which strongly suggests that Thunderbolt 5, like its predecessors, will use a USB-C connector.
Thunderbolt was first released in 2011 and is Intel’s high-speed connection standard. The standard is currently on Thunderbolt 4, although it offers the same 40 Gbps bandwidth and feature set as Thunderbolt 3. By doubling the bandwidth to 80 Gbps, Thunderbolt 5 has the potential to provide higher refresh rates for 4K and 8K displays, which now support up to 120 and 60 Hz, respectively.
In order to achieve higher bandwidth on Thunderbolt 5, it seems that the protocol will use PAM-3 modulation, which is an unusual method. So far, in protocols such as USB and PCIe, we have seen non-return-to-zero (NRZ) and PAM-4 (pulse amplitude modulation) implementations. The NRZ signal is binary, which means there are only 0 and 1, while the PAM-4 signal is expressed in a two-bit format, which is a combination of 0 and 1 (for example, 01, 11, 11, 00).For a more detailed explanation, please check This blog.
The novel PAM-3 uses -1, 0, and +1 states. This method is located right between NRZ and PAM-4, but it allows the realization of this signaling technology to be much simpler than PAM-4 while maintaining high bandwidth. With PAM-3, implementation should be easier and more efficient, so Intel calls it the “novel PAM-3” approach.
The leaked slide also pointed out that “…the N6 test chip focused on the new PHY technology is…showing promising results.” Although we can’t see the complete slide, it means that the Thunderbolt 5 PHY (physical layer) is already working in the fab and is producing the expected results. We know that N6 is TSMC’s 6 nm manufacturing node. We can assume that Intel uses TSMC’s foundry to manufacture Thunderbolt 5 test chips.