JEDEC has Publish The new revision of the LPDDR5 standard (JESD209-5B) covers some performance and power improvements to the original specification and LPDDR5X. LPDDR5X is an extension of LPDDR5 that increases the maximum data transfer rate to 8533 MT/s. LPDDR5 and LPDDR5X will coexist and complement each other in the market.
LPDDR5 and LPDDR5X are pin compatible, which greatly simplifies the development of system-on-chip (SoC) and platforms that support new types of memory. In order to achieve a higher data transfer rate and improve the reliability of the upcoming low-power memory subsystem, LPDDR5X introduces a pre-emphasis function to increase the signal-to-noise ratio (to achieve higher clock and performance improvements) and reduce the bit error rate As an adaptive refresh management and per-pin decision feedback equalizer (DFE) to enhance the robustness of the memory channel (taken from a page of the DDR5 standard).
LPDDR5 has a data rate of up to 6400 MT/s, so LPDDR5X provides a 33% strong performance improvement with its 8533 MT/s data. Performance enhancements will be welcomed by applications that require bandwidth, such as AI/ML and graphics processing. In addition, if LPDDR5X gains support for PC SoC, these computers may gain memory bandwidth that even machines with DDR5 memory cannot access, which would be a huge benefit, especially for integrated graphics.
So far, LPDDR5X has been approved by Micron and Samsung, so expect these companies to provide suitable chips when needed. At the same time, Synopsys will provide IP (Memory Controller, PHY) to enable SoC developers to add support for LPDDR5X in their designs.
“In synchrony with JEDEC’s LPDDR5/5X standardization process, Samsung has also been working closely with leading manufacturers to pave the way for the next generation of smartphones, laptops and other mobile computing devices,” said Doohee Hwang, chief engineer of mobile DRAM product planning, Samsung electronic.
Since the LPDDR5X proposal has been around for some time, it is reasonable to expect that SoC designers and actual hardware manufacturers will adopt new memory standards sooner or later, especially considering that modern SoCs have high bandwidth requirements for high-performance applications. However, it is difficult to say what we are. At that time, we will see the first batch of devices that support LPDDR5X on the market.
Osamu Nagashima, Senior Manager of Micron Mobile System Architecture and JEDEC Vice Chairman, said: “As a leader in the field of low-power memory, Micron has worked closely with other JEDEC members to define LPDDR5X, providing a key advancement for the mobile ecosystem with higher bandwidth. Low Power Memory Subcommittee. “The high-speed interface of LPDDR5X will open the door to new 5G and AI use cases, providing a better user experience for memory-intensive applications such as games, photography, and streaming. “