PCI-SIG this week Announce The PCIe 6.0 specification has reached the final draft status, which is an important milestone that officially marks the completion of development. All system-on-chips that comply with PCIe 6.0 version 0.9 specification will comply with the final 1.0 version of the technology. The only question is which applications actually require PCIe Gen6.
PCIe Gen6 will increase the data transfer rate from 32 GT/s of PCIe Gen5 and 16 GT/s of PCIe Gen4 to 64 GT/s per pin, but will maintain backward compatibility with existing hardware. The new technology allows up to 128 GB of data to be transferred per second in each direction via the x16 interface.
PCI Express The specification has five main checkpoints: Concept, First Draft, Complete Draft, Final Draft and Final.’S release PCIe 6.0 complete draft (Version 0.7) The specification enabled large companies and technologies less than a year ago Developers like Synopsys Started to implement their PCIe 6.0 controller IP and PHY in silicon. The release of the PCIe 6.0 final draft (version 0.9) specification marks a point after which no functional changes are allowed, and PCI-SIG members should begin to review their intellectual property and patent standards.
Companies that manage to incorporate PCIe 6.0 v0.9 support into their system-on-chip (SoC) can theoretically start selling them as “PCIe 6.0 Ready”, but they will not be able to officially confirm compatibility with the final PCIe 6.0 version 1.0 specification. Because there is currently no formal PCIe 6.0 compliance plan, and no PCIe 6.0 compliance seminars are held.
In order to make such extreme data transfer rates and bandwidths possible, developers of new standards must use pulse amplitude modulation with four-level signaling (PAM-4), which is also used in high-end network technologies such as InfiniBand and GDDR6X memory. In addition, PCIe Gen6 has a low-latency forward error correction (FEC) function to ensure high efficiency at high data rates.
Although PCIe 6.0 is an important step forward for the interface because it brings many innovations and significantly improves performance, it will also bring many challenges to chip and system designers. First of all, PAM-4 is always expensive in terms of power and chip size, which is why it has not been widely adopted over 100GbE and 200GbE high-end data center or enterprise network standards. Secondly, 64 GT/s is a very high data transmission rate. Although PAM-4 with FEC will help alleviate some difficulties, the signal transmission on the printed circuit board (PCB) must be optimized for crosstalk, loss, and reflection. And power integrity.
Essentially, this means that not all SoC designers (especially in the field of client PCs) are eager to adopt PCIe 6.0 due to cost and power consumption issues. In addition, implementing PCIe 6.0 at the system level will require complex PCBs and frequent use of expensive retimers and redrivers over relatively short distances. All in all, although PCIe 6.0 makes sense for servers and dedicated systems, it may be too expensive for the widespread use of client PCs, so consumer GPU and SSD controllers may adopt it.