At Hot Chips 2021, Synopsys announced an ambitious plan to develop a fully integrated set of electronic design automation (EDA) tools that rely on artificial intelligence. These tools are expected to reduce chip development costs, shorten time to market, improve performance and increase yield. Samsung has received the first chip designed with AI-assisted EDA tools and found that its performance is better than expected, while power consumption is lower.
Optimize the physical layout
The physical design of modern chips is an expensive and difficult process. As the manufacturing technology becomes thinner and thinner, the cost of IC design is also rising. Nowadays, it takes years to develop a new CPU or GPU architecture, and the physical realization of the design chip may take about 24 months or more. Some analysts said that in 3nm design, the cost of complex GPU will be close to 1.5 billion US dollars, not all companies can afford it. However, Synopsys says there is a way to use AI-enabled design tools to reduce these costs by as much as 50% and reduce development time by orders of magnitude.
Modern EDA tools have greatly simplified chip development, but chip floor plans, layout, layout, and routing require input from human engineers who use their experience to develop efficient designs. Every small aspect of chip design requires people to evaluate different design options and make multiple decisions. Although experienced engineers often work very fast, they cannot evaluate hundreds of design options within a reasonable time, explore the feasibility of all possible combinations, and then simulate dozens or even hundreds of different layouts to find the best Layout. In contrast, the Synopsys DSO.ai platform can do this, with one notable exception: it does not have to simulate all 10^90,000 possible IC placement and routing methods, because it can use artificial intelligence to find the best way .
Synopsys’ DSO.ai is compatible with the company’s EDA tools, and promises to optimize all PPA (performance, power, area) aspects of chip design in a timely manner, which is impossible for today’s human engineers. For example, the test chip designed by Synopsys using AI-assisted software has a 26% reduction in power consumption compared to the same chip designed by a human engineer, and the machine only needs a small amount of time. In order to achieve this goal, Synopsys DSO.ai optimized the geometry, architecture selection points and related physical layout, as well as the behavior of the chip.
Synopsys’ DSO.ai algorithm is compatible with all process technologies, so as the complexity of IC design increases, their value will increase over time. Synopsys said that due to the use of AI, chip design (placement and routing) time may be reduced from 24 months today to 24 weeks.
Samsung is the first company to use the Synopsys DSO.ai platform for chip design and has already received its working IC from the fab. Google and Nvidia also chose DSO.ai, so expect these companies to accelerate chip development and reduce design costs.
However, physical (layout) design and layout planning are not the only chip development steps that can use artificial intelligence aids. To build an IC, developers must design the architecture, structure, floor plan, and layout. Usually, creators use the so-called waterfall semiconductor design method and develop each step individually.
Synopsys said that this traditional method has many shortcomings, which will negatively affect the chip design process and make it longer (through architecture development, it takes at least three years to build a modern chip), because the design options are not limited by the design options. Simultaneous evaluation of human engineers.
EDA tool manufacturers recommend that chip manufacturers adopt a new cyclone design model, which will use AI-assisted software to evaluate all key elements of the chip in parallel to optimize all aspects of semiconductor design for optimal performance, power consumption, and cost . Quite a short time. Synopsys said that the Cyclone chip design method can shorten the chip development time to two or three months and increase the designer’s work efficiency by 1,000 times, which will reduce the number of engineers involved in chip design.
Reducing SoC development time and the number of engineers required will allow small companies that currently cannot afford to develop their own processors to enter the market and provide tailored solutions for applications that currently rely on general-purpose hardware.
Synopsys admits that using AI-assisted EDA tools requires considerable computing power and is expensive. Big companies like Google or Nvidia have quite powerful data centers for analog architectures and circuits, so nothing will change for them. For smaller players, Synopsys is considering providing AI auxiliary tools in the cloud, which will further reduce chip design costs.
Synopsys’ DSO.ai software enables chip developers to reduce power consumption, improve performance, reduce chip size, and shorten semiconductor development time. This is a big problem because physical designs are becoming increasingly difficult to implement, and their complexity will only increase in the next few years. As the industry transitions to 3nm manufacturing processes and GAAFET transistors, chip design costs will increase dramatically, so artificial intelligence-assisted EDA tools will become critical for large chip developers.
However, artificial intelligence-assisted physical design tools are only the tip of the iceberg of artificial intelligence in chip development. Synopsys claims that the traditional waterfall method of semiconductor design does not allow engineers to evaluate different architectures and design options at the same time, which increases cost and time to market. EDA believes that molybdenum’s overall cyclone design model and software-designed hardware will enable developers to significantly reduce design time and cost, which will open the door to chip development for companies that could not afford it before.