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Synopsys uses HBM3 to implement 5nm SoC

Synopsys this week Unveil Its HBM3 solution enables system-on-chip (SoC) developers to add support for next-generation HBM3 memory to 2.5D designs implemented using a 5nm manufacturing process. The IP package supports HBM3 memory chips with a capacity of up to 64GB, a data transfer rate of up to 7200 MT/s, and a bandwidth of up to 921 GB/s.

Leading memory manufacturers Micron, Samsung, and SK Hynix have recognized Synopsys’ industry’s first complete HBM3 solution and expressed their commitment to producing HBM3 memory. Synopsys’ HBM3 solution includes DesignWare HBM3 controller, physical interface (PHY), verification IP and 3DIC compiler.

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