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Synopsys this week Unveil Its HBM3 solution enables system-on-chip (SoC) developers to add support for next-generation HBM3 memory to 2.5D designs implemented using a 5nm manufacturing process. The IP package supports HBM3 memory chips with a capacity of up to 64GB, a data transfer rate of up to 7200 MT/s, and a bandwidth of up to 921 GB/s.
Leading memory manufacturers Micron, Samsung, and SK Hynix have recognized Synopsys’ industry’s first complete HBM3 solution and expressed their commitment to producing HBM3 memory. Synopsys’ HBM3 solution includes DesignWare HBM3 controller, physical interface (PHY), verification IP and 3DIC compiler.
The Synopsys HBM3 controller supports up to 32 pseudo channels (that is, 16 physical 64-bit channels or a 1024-bit interface), each with 16 to 64 groups and a channel density of up to 32Gb. More practically speaking, a controller with PHY supports HBM3 memory stacks with different numbers of layers, with a capacity of up to 64 GB and a 1024-bit physical interface transfer rate of up to 7200 MT/s of data. A typical HBM supports SoC with two, four, or six controllers. Therefore, Synopsys’ HBM3 solution can provide up to 3.68 TB/s of memory bandwidth for an SoC equipped with four HBM3 stacks.
The controller also supports error correction code (ECC), refresh management, and parity checking, so it can be used in data centers and high performance computing (HPC) applications that require various RAS (reliability, availability, scalability) functions.
Synopsys said its HBM3 controller and PHY Mainly based on the company’s HBM2E IP verified by 5nm silicon, which means risk reduction. At the same time, Synopsys’ HBM3 controller uses the proven DFI 5.0 interface to connect to its PHY and supports the widely used Arm multi-port AMBA 4 AXI host interface.
In order to further simplify implementation and reduce risks, the company provides 3DIC Compiler, which has a complete HBM3 automatic routing solution that enables fast and robust design development.
“Synopsys continues to meet the design and verification requirements of data-intensive SoCs, providing high-quality memory interface IP and verification solutions for the most advanced protocols such as HBM3, DDR5, and LPDDR5,” said John Koeter, senior vice president of marketing and strategy. Synopsys’ IP. “The complete HBM3 IP and verification solution enables designers to meet increasing bandwidth, latency and power requirements while accelerating verification closure, all from a trusted supplier.”
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