TSMC, in VLSI Seminar, Recently Introduce its research on on-chip water cooling As a way to solve the heat dissipation problem. It involves integrating the water channel directly into the design of the chip.
Due to denser manufacturing techniques and increased vertical 3D chip stacking, transistors are increasingly compressed together, and temperature has become an increasingly critical issue that needs to be solved. Researchers at TSMC believe that the solution is to allow water to flow between the mezzanine circuits. This is a very simple theoretical solution, but for electronic products, it is an extremely difficult engineering feat.
The math is simple: current cooling solutions usually work through direct contact with the heat sink of a given chip, direct chip contact technology, or complete immersion in a non-conductive fluid. Among them, the first two solutions can only effectively cool the layers they directly contact, which brings huge problems to vertical chip stacking. The lower layer will encounter more difficulties in heat dissipation, will cause damage or have to throttle, both of which will be detrimental to performance.
Not only that, because the heat of the entire package must be transferred to the heat dissipation layer, the top layer of the chip will increase pressure. Although liquid immersion is efficient and may be more suitable for stacking chips, it is expensive and difficult to deploy in professional scenes that are already suitable for air cooling or traditional water cooling.
TSMC tested virtual semiconductors under controlled laboratory conditions-a thermal test carrier (TTV), which is essentially a heating element made of copper. The company tested three types of silicon water channel integration under controlled conditions: it uses column-based channels where water can flow around active semiconductor columns to cool them (think about the water around the island); the trench design is Characteristic design (imagine a river, controlled by its shore); and simple and flat waterways in the rest of the silicon chip. The water passes through an external cooling mechanism that cools the water to 25 ºC as it passes through the silicon chip.
The company further tested three types of water-cooling designs: one with only direct water-cooling (DWC), as part of the manufacturing process, the water has its own circulation channel directly etched into the silicon of the chip; the other design etched the water channel to the top of the chip In its own silicon layer, a thermal interface material (TIM) layer of OX (silicon oxide fusion) is used to transfer heat from the chip to the water cooling layer; finally, a design that replaces the OX layer with a simpler and cheaper liquid metal solution .
TSMC reported that the current best solution is direct water cooling, which can dissipate up to 2.6 kW of heat and provide a temperature difference of 63 ºC. The second best design is naturally based on the OX TIM design, which can still dissipate up to 2.3 kW of heat and provide a temperature difference of 83 ºC. The liquid metal solution came last and still managed to dissipate up to 1.8 kW (75 ºC temperature increase). Among all the water flow designs, the column design is by far the best.
Of course, mainstream adoption of this peculiar cooling solution will take several years. But this is definitely one of the directions for realizing the continuous increase in transistor density, the continuous improvement of performance indicators in each area, and the future of 3D semiconductors.