The Moore’s Law journey is a technologically complex and expensive journey, multi-billion-dollar R&D-just ask the semiconductor manufacturer. The well-known “soft” law created by Intel co-founder Gordon Moore states that the number of transistors in densely packaged semiconductors should double every two years. The demise of Moore’s Law has been hailed time and time again, and is now understood more as a goal than a rule-but it is a necessary goal for silicon designers to compare. However, the ever-increasing density of transistors presents many challenges to system designers-physics and current state of the art always have limitations that define the hard limit on how many transistors can be pushed into a single chip. As transistor density and chip size increase, the impact of manufacturing defects (which may render some chips unusable) must also be taken into consideration.
Semiconductor designs for decades have favored monolithic monolithic chips, until AMD demonstrated the powerful features of its Zen-based chiplets—in essence, AMD pioneered the mainstream use of smaller semiconductor “blocks” (in Zen, CCX (Or Core Complex as a representative) and then glued together (in Intel’s own words) together into the final chip, interconnected by AMD’s own Infinity Fabric (responsible for transferring information from one chiplet to another). This bypasses some of the limitations of currently available semiconductor manufacturing processes, because smaller chips are less likely to have manufacturing defects, and allow chip designers to better distribute computing resources to account for the density of transistors and these closely packed together. Achieve a better balance between heat components. Even if chiplets are becoming more and more popular in the industry and may become the new de facto standard for performance expansion (Nvidia and Intel have also been exploring chiplets and MCM [Multi-Chip Modules] For future products), there are still some players looking for new ways to improve chip performance density, such as Cerebras, which has 2.3 trillion transistors, 850,000 cores and 15 kW power requirements. Wafer level engine 2.
The Wafer Scale Engine is the largest chip in the world, and as you can guess from the dizzying statistics, it itself shames some supercomputers. The purpose of deciding to adopt the wafer scale is to solve one of the problems caused by the deployment of more and more independent chips working together-they must communicate with each other, understand where the information is, what processing state the data is in, and transmit it to The next processing step. Keeping everything in a single chip means shortening the distance between different ICs and enabling Cerebras to develop its own interconnect technology (similar to AMD’s Infinity Fabric) that can transmit at speeds up to 220 Petabits/S data. However, Cerebras’ Wafer Scale Engine is still essentially a monolithic chip, which means that it still faces the same limitations as them—especially a larger surface area for manufacturing defects. Although the company has built-in additional resources in the chip design to alleviate these problems-that is, additional cores and IC components that can replace cores and IC components that are disabled due to manufacturing defects-they still need to be considered when designing at this point. Talking about the future of computing. However, the experience learned from Cerebras’ design is likely to be applied to future wafer-level computing solutions.
One such solution A perfect theoretical combination between wafer-level design and a more cost-effective chiplet approach (wafer-level chips based on chiplets) is proposed. The idea is simple: based on Cerebras’ innovation-a wafer-sized substrate that enables interconnection between all components-instead of engraving a monolithic chip from it, you “simply” add a chip-based chip on top The blocks are interconnected. What I said is very simple, because the work of bonding multiple ICs on a substrate is more complicated than it sounds. Even so, this will allow future chip designers to utilize and combine multiple, possibly even different pieces of silicon into a wafer-sized chip, thereby increasing yield and overall chip cost. Imagine a wafer-level engine made by AMD that combines multiple Zen 3 CCX and graphics chips, Xilinx-based FPGAs, Arm cores, and anything else you can think of-just deployed on a wafer-sized substrate.
This actually coincides with the thought process taken Discussing wafer-level chips for the first time in the scientific community, Written by Saptadeep Pal and colleagues; Wafer-level chip design based on the concept of heterogeneous computing. Even if it is as powerful as Cerebras’ Wafer Scale Engine, it is already dealing with the endless pits of global computing power demand. Rakesh Kumar, a wafer-level collaborator at the University of Illinois and Pal, described the entire heterogeneous wafer-level design as: “The chiplet-based approach allows heterogeneous integration of technology on the wafer. This means wafer-level processing based on chiplets The high-density memory (such as DRAM, flash memory, etc.) can reside on the same processor. This can achieve better memory capacity characteristics than the Cerebras method, which cannot support heterogeneous technologies on the processor, thereby limiting processing The memory capacity of the processor. This is critical for many applications, including many ML models, whose application requirements far exceed those provided by Cerebras processors.”
The best part? Such a design can already be achieved using today’s technology. Proving Moore’s Law again seems to be only a matter of time.